1. Field of the Invention
The present invention relates to a control technique for controlling a plurality of memory devices.
2. Description of the Related Art
Recently, in the field of LSIs, a generally practiced design technique is a technique called SOC (System On a Chip) of integrating necessary functions (systems) on one semiconductor chip.
In a semiconductor chip designed by SOC, many fast large-capacity memory devices are generally mounted on the semiconductor chip to allow concurrent processing of each functional block (Intellectual Property) mounted on the chip. More specifically, many memory devices mounted on the chip include SDRAMs, DDRs, SDRAMs, and DDR2SDRAMs.
A reduction in power consumption is an important challenge for a semiconductor chip on which many memory devices are mounted in the above manner. Various proposals have been made to this end.
For example, Japanese Patent Laid-Open No. 9-180438 discloses a control method of reducing power consumption by setting a memory device in a low power consumption state such as a self-refresh mode or a power-down mode.
According to Japanese Patent Laid-Open No. 9-180438, however, a plurality of memory devices mounted on a semiconductor chip are configured to be controlled collectively. This makes it impossible to obtain a sufficient effect in terms of reducing power consumption in a semiconductor chip on which many memory devices like those described above which can be independently accessed using chip select (CS) signals are mounted.
For this reason, when many memory devices are mounted on a chip, Nop (No operation) commands are generally used to individually switch devices between a low power consumption mode and a normal mode. More specifically, controlling the Low/High level of a CKE (clock enable) signal accompanying the issuance of a Nop command allows to switch each memory device between the low power consumption mode and the normal mode.
FIG. 17 shows a simplified timing chart for a case in which a Nop command is used to switch each memory device between the low power consumption mode and the normal mode. Switching between the low power consumption mode and the normal mode will be briefly described below with reference to FIG. 17.
Referring to FIG. 17, reference numeral 1701 denotes a clock (CLK) signal; 1702, access command; 1703, a chip select (CS) signal; and 1704, a clock enable (CKE) signal.
In the case of FIG. 17, the CS signal 1703 is first set to Low to activate the memory device, and a write command Wr is then issued to write the corresponding write data in the memory device. Issuing a Nop command after the transmission of the write command Wr will make the memory device start “PowerDown” to shift to the low power consumption mode.
More specifically, upon issuance of a Nop command, the CKE signal 1704 is set to Low to make the memory device start “PowerDown” at a first leading edge timing t1 of the CLK signal 1701 thereafter to shift to the low power consumption mode.
Note that setting the CS signal 1703 at High after the issuance of a Nop command 1711 will inactivate the memory device. The inactive state continues until the next access command is issued.
In this case, when the next write command is to be issued, it is necessary to make the memory device end “PowerDown” to shift to the normal mode in advance. That is, it is necessary to set the CKE signal 1704 at High a predetermined number of clocks before the timing of issuing the next write command.
For this purpose, the CS signal 1703 is set to Low again at a timing t3 to activate the memory device, and a Nop command is issued while the CKE signal 1704 is set to High. The memory device ends “PowerDown” at a first leading edge timing t4 of the CLK signal 1701 after the CKE signal 1704 is set to High. The memory device then shifts to the normal mode.
Subsequently, issuing a write command will write corresponding write data in the memory device.
In this manner, in a memory device configured to control switching between the low power consumption mode and the normal mode by using a Nop command, switching is performed by activating the memory device using a CS signal and issuing a Nop command.
When a plurality of memory devices are mounted on a chip, therefore, a Nop command is issued to each memory device which switches between the low power consumption mode and the normal mode.
FIG. 18 is a timing chart for a case of switching between the low power consumption mode and the normal mode of each of four memory devices (first to fourth memory devices) mounted on a semiconductor chip.
Referring to FIG. 18, reference symbols CS0 and CKE0 denote a CS signal and a CKE signal for the first memory device, respectively; and CS1 to CS3 and CKE1 to CKE3, CS signals and CKE signals for the second to fourth memory devices, respectively.
In the case of FIG. 18, after the CS signals are set to Low, write commands are sequentially issued to the first to fourth memory devices. In this case, issuing Nop commands before and after the issuance of write commands will implement low power consumption mode/normal mode switching.
More specifically, the first memory device performs the write processing of write data from t2 to t6. Thereafter, the memory device starts “PowerDown” at a timing t10. The memory device is set in the low power consumption mode until the end of “PowerDown” at a timing t21.
Likewise, in the second to fourth memory devices, the write processing of write data and low power consumption mode/normal mode switching are performed for the respective memory devices at different timings.
As indicated by the timing chart of FIG. 18, however, switching between the low power consumption mode and the normal mode for each memory device by using a Nop command will inevitably degrade the access efficiency of each memory device.
This is because it is necessary to issue a Nop command when issuing a “PowerDown” start/end command to each of a plurality of memory devices mounted on a chip. That is, the issuance of a Nop command will delay the timing of the issuance of an access command such as a write command.
As described above, when each memory device is configured to switch between the low power consumption mode and the normal mode by using a Nop command, the access efficiency degrades as the switching frequency increases (the reduction of power consumption increases).